Architecture of a High-Performance Image Processing System
نویسندگان
چکیده
This paper describes the architecture of a high performance, compact image processing system. The system feature is that an image processor is constructed by employing eight kinds of high speed VLSIs, including real-time video image processing LSI(1SP-11). These VLSIs are developed while realizing both compactness and easy system extensions. The ISP-I1 is a VLSI for gray scale image processing. It includes two line buffer memories and has a time-shared processing function. So one ISP-I1 can carry out a 3 x 3 spatial convolution at 6 MHz without additional circuitry. Using three ISP-IIs, a 3 x 3 spatial convolution can be executed at 24 MHz. The system's image processor is realized on one board, including three gray 8-bit and three binary image memories having 5 12 x 5 12 pixels, A D and D/A converters, etc. The image processing speed is 6 MHz in processing a 3 x 3 spatial convolution, labeling, etc., and 12 MHz in executing a n affine transform, inter-image processing, etc.
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تاریخ انتشار 1988